A timing-recovery circuit uses data transitions to adjust the phase of the sampling receiver clocks at the center of the data symbol, i.e., the “eye opening.” There are two main approaches for timing recovery from a serial data: oversampling data recovery and tracking phase detection.
In the oversampling technique, each transmitted symbol is sampled N times (N≧3), and the sample that is closest to the symbol center is selected by logic as the data. See, for example, C.-K. Yang, R. Farjad, M. Horowitz, “A 0.5-mm CMOS 4-Gbps Serial Link Transceiver,” IEEE JSSC, vol. 33, no. 5, May 1998. This approach allows very fast timing recovery, but suffers from large input loading (due to the large number of samplers), and phase quantization error (due to limited number of samples per symbol). Furthermore, it requires complex logic to process many samples at high frequency that dissipates large area and power.
In the tracking phase detection technique, a data phase detector measures the phase difference between the transition edge of the transmitted symbol and the sampling clock, typically by directly measuring the difference between the transition's zero-crossing and the clock pulse. This error value is used to align the sampling point at the symbol center. There are two general approaches for tracking phase detection: bang-bang phase correction and proportional phase error correction.
In bang-bang phase correction, the current status of a system is compared with a target status. In response to any measured error, the system is corrected each cycle by adding or subtracted a fixed amount of phase, according to the polarity of the error.
In proportional phase error correction, on the other hand, the system is corrected not by a fixed amount, but rather by an amount that is proportional to the measured error.
Traditional proportional tracking data phase locked loops (PLLs) offer good loop stability and bandwidth, but they typically require front-end circuits to operate at the same speed as the input serial data rate, which is one of the major bottlenecks for achieving higher speeds in a certain process technology. In addition, most proportional phase detectors potentially suffer from a systematic phase offset, because the manner in which they extract information from data transitions differs from the way they sample the data center. See Thomas H. Lee and John Bulzacchelli, “A 155-MHz Clock Recovery Delay and Phase-Locked Loop,” IEEE JSSC, December 1992; Mehmet Syuer, “A Monolithic 2.3-Gbps 100-mW Clock and Data Recovery in Silicon Bipolar Technology,” IEEE JSSC, December 1993; and Jafar Savoj and Behzad Razavi, “A 10-Gbps CMOS Clock and Data Recovery Circuit,” Digest of technical papers, VLSI Symposium June, 2000.
Sampling transitions with the same mechanism used to sample the symbol centers eliminates the systematic phase offset in data recovery, and this approach has been used in sampling digital loops. See, for example, Timothy Hu and Paul Gray, “A Monolithic 480 Mb/s AGC/Decision/Clock-Recovery Circuit in 1.2-mm CMOS,” IEEE JSSC, vol. 28, no. 12, December 1993; and Alan Fielder, et al, “A 1.0625 Gbps Transceiver with 2×-Oversampling and Transmit Signal Pre-emphasis,” Digest of technical papers, ISSCC February 1997. However, conventional sampling digital loops use bang-bang control, resulting in limited bandwidth and stability, not to mention metastability in samplers when sampling at zero crossings.